We have developed a novel MEMS based interposer which severs as the electromechanical interface between the device chip under test (DUT), and the test processor. It is capable of fanning out of 100 /spl mu/m pitch I/Os to 750 /spl mu/m pitch pads which is compatible with conventional PCB technology. The interposer has both power and ground planes near the signal traces to enable the high frequency transmission. It was fabricated on a silicon substrate using semiconductor and micro-machining processes. Through wafer vias were formed by KOH anisotropic etching. Conductive materials were filled in the vias to form interconnection. The interposer also has compliant structures which give vertical compliance to the probe pads. Because silicon substrate is used, there is no thermal mismatch, which gives our interposer the potential of being used in wafer level burn-in test.
[1]
W. F. Schmidt,et al.
A simple technique for determining yield strength of thin films
,
2002
.
[2]
Design and fabrication of a monolithic high-density probe card for high-frequency on-wafer testing
,
1989,
International Technical Digest on Electron Devices Meeting.
[3]
M. Ueda,et al.
A fine pitch probe technology for VLSI wafer testing
,
1990,
Proceedings. International Test Conference 1990.
[4]
F. Matta,et al.
Wafer-level testing with a membrane probe
,
1989,
IEEE Design & Test of Computers.
[5]
Nicholas Sporck.
A new probe card technology using compliant Microsprings/sup TM/
,
1997,
Proceedings International Test Conference 1997.