Achieving Design Closure Through Delay Relaxation Parameter

Current design automation methodologies are becoming incapableof achieving design closure especially in the presence of deep submicroneffects. This paper addresses the issue of design closure from ahigh level point of view. A new metric called delay relaxation parameter(DRP) for RTL (Register Transfer Level) designs is proposed. DRPessentially captures the degree of delay relaxation that the design cantolerate without violating the clock constraint. This metric when optimizedresults in quicker design flow. Algorithms to optimize DRP areformulated and their optimality are investigated. Experimental resultsare conducted using a state of the art design flow with Synopsys DesignCompiler followed by Cadence Place and Route. Our approachof optimizing DRP resulted in lesser design iterations and faster designclosure as compared to designs generated through Synopsys BehavioralCompiler and a representative academic design flow.