EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate

Faulty cell repair with redundancy can improve memory yield. In particular, built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. We propose an efficient BIRA algorithm to achieve the optimal repair rate with a very short analysis time and low hardware cost. The proposed algorithm can significantly reduce the number of backtracks in the exhaustive search algorithm: it uses early termination based on the number of orthogonal faulty cells and fault classification in fault collection. Experimental results show that the proposed BIRA methodology can achieve optimal repair rate with low hardware overhead and short analysis time, as compared to previous BIRA methods.

[1]  W. Kent Fuchs,et al.  Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.

[2]  Fabrizio Lombardi,et al.  New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[4]  Joao Marques-Silva,et al.  Robust search algorithms for test pattern generation , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[5]  Hung-Yau Lin,et al.  An efficient algorithm for spare allocation problems , 2006, IEEE Transactions on Reliability.

[6]  Jin-Fu Li,et al.  ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  A. C. Dumbri,et al.  A 256K dynamic random access memory , 1982, IEEE Journal of Solid-State Circuits.

[8]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Janak H. Patel,et al.  New Techniques for Deterministic Test Pattern Generation , 1999, J. Electron. Test..

[10]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  John Day.  A Fault-Driven, Comprehensive Redundancy Algorithm , 1985, IEEE Design & Test of Computers.

[12]  Kwang-Ting Cheng,et al.  A circuit SAT solver with signal correlation guided learning , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[13]  Hans-Joachim Wunderlich,et al.  An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy , 2007, 12th IEEE European Test Symposium (ETS'07).

[14]  Joao Marques-Silva,et al.  GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.

[15]  Yu-Jen Huang,et al.  A Built-In Self-Repair Scheme for Multiport RAMs , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[16]  Ofer Strichman,et al.  Pruning Techniques for the SAT-Based Bounded Model Checking Problem , 2001, CHARME.

[17]  Sudhakar M. Reddy,et al.  On the Repair of Redundant RAMs , 1989, 26th ACM/IEEE Design Automation Conference.

[18]  C.L. Liu,et al.  Fast search algorithms for reconfiguration problems , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[19]  Jin-Fu Li,et al.  A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs , 2006, 2006 IEEE International Test Conference.

[20]  Chin-Long Wey,et al.  On the Repair of Redundant RAM's , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Rolf Drechsler,et al.  Test Pattern Generation using Boolean Proof Engines , 2009 .

[22]  Sungho Kang,et al.  High-efficiency memory BISR with two serial RA stages using spare memories , 2008 .

[23]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[24]  R.P. Cenker,et al.  A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.

[25]  Rubin A. Parekhji,et al.  On-chip Test and Repair of Memories for Static and Dynamic Faults , 2006, 2006 IEEE International Test Conference.

[26]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[27]  Wilfried Daehn,et al.  Contest: a fast ATPG tool for very large combinational circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[28]  Rolf Drechsler,et al.  On Acceleration of SAT-Based ATPG for Industrial Designs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  R. G. Nelson,et al.  Laser programmable redundancy and yield improvement in a 64K DRAM , 1981 .

[30]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[31]  Michael S. Hsiao,et al.  ALAPTF: a new transition fault model and the ATPG algorithm , 2004, 2004 International Conferce on Test.

[32]  Sudhakar M. Reddy,et al.  TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis , 2009, 2009 22nd International Conference on VLSI Design.

[33]  Swapnil Bahl.  A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[34]  Christoph Scholl,et al.  Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets , 2007, 2007 Asia and South Pacific Design Automation Conference.

[35]  Sungho Kang,et al.  A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[36]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  Hideo Fujiwara,et al.  SPIRIT: a highly robust combinational test generation algorithm , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.