A High-Performance Sum of Absolute Difference Implementation for Motion Estimation

This paper presents a high-performance sum of absolute difference (SAD) architecture for motion estimation, which is the most time-consuming and compute-intensive part of video coding. The proposed architecture contains novel and efficient optimizations to overcome bottlenecks discovered in existing approaches. In addition, designed sophisticated control logic with multiple early termination mechanisms further enhance execution speed and make the architecture suitable for general-purpose usage. Hence, the proposed architecture is not restricted to a single block-matching algorithm in motion estimation, but a wide range of algorithms is supported. The proposed SAD architecture outperforms contemporary architectures in terms of execution speed and area efficiency. The proposed architecture with three pipeline stages, synthesized to a 0.18-mum CMOS technology, can attain 770-MHz operating frequency at a cost of less than 5600 gates. Correspondingly, performance metrics for the proposed low-latency 2-stage architecture are 730 MHz and 7500 gates

[1]  Kai-Kuang Ma,et al.  Correction to "a new diamond search algorithm for fast block-matching motion estimation" , 2000, IEEE Trans. Image Process..

[2]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[3]  Amos R. Omondi,et al.  Computer arithmetic systems - algorithms, architecture and implementation , 1994, Prentice Hall International series in computer science.

[4]  T Koga,et al.  MOTION COMPENSATED INTER-FRAME CODING FOR VIDEO CONFERENCING , 1981 .

[5]  Olli Lehtoranta,et al.  Complexity analysis of spatially scalable MPEG-4 encoder , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[6]  Stamatis Vassiliadis,et al.  The sum-absolute-difference motion estimation accelerator , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

[7]  Liang-Gee Chen,et al.  An efficient and simple VLSI tree architecture for motion estimation algorithms , 1993, IEEE Trans. Signal Process..

[8]  Konstantinos Konstantinides,et al.  Image and Video Compression Standards: Algorithms and Architectures , 1997 .

[9]  Kai-Kuang Ma,et al.  A new diamond search algorithm for fast block-matching motion estimation , 2000, IEEE Trans. Image Process..

[10]  Peter Kuhn,et al.  Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation , 1999, Springer US.

[11]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[12]  Hongyi Chen,et al.  An efficient implementation of motion estimation algorithms , 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.