Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design
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[1] Steven M. Nowick. Design of a low-latency asynchronous adder using speculative completion , 1996 .
[2] Simon Knowles,et al. A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).
[3] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[4] Naresh R. Shanbhag,et al. Soft digital signal processing , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[5] Michael S. Waterman,et al. An extreme value theory for long head runs , 1986 .
[6] Behrooz Parhami,et al. Computer arithmetic - algorithms and hardware designs , 1999 .
[7] Israel Koren. Computer arithmetic algorithms , 1993 .
[8] Harold S. Stone,et al. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.
[9] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[10] Krishna V. Palem,et al. Probabilistic arithmetic and energy efficient embedded signal processing , 2006, CASES '06.
[11] Mark Schilling,et al. The Longest Run of Heads , 1990 .
[12] Jianhua Liu,et al. Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space , 2007, 2007 Asia and South Pacific Design Automation Conference.