Hardware synthesis of complex system-on-chip designs for embedded systems using a behavioural programming and multi-process model

Embedded Systems used for control, for example in Cyber-Physical-Systems (CPS), perform the monitoring and control of complex physical processes using applications running on dedicated execution platforms in a resource-constrained manner. Application-specific System-On-Chip (SoC) designs providing the execution platform have advantages compared with traditionally used program-controlled multiprocessor architectures. SoC designs can be modelled on structural and behavioural level. The behavioural level is generally a more sophisticated modelling level. In the context of CPS, these are mainly reactive systems with dominant and complex control paths. The major contribution to concurrency appears on control path level. A new SoC design methodology is presented using the behavioural hardware compiler ConPro providing an imperative programming model based on concurrently communicating sequential processes (CSP) with an extensive set of interprocess-communication primitives and guarded atomic actions. The programming language and the compiler-based synthesis process enables the design of constrained powerand resource-aware embedded systems with pure RegisterTransfer-Logic efficiently mapped to FPGA and ASIC technologies. Concurrency is modelled explicitly on controland datapath level. Additionally, concurrency on datapath level can be explored and optimized automatically by different schedulers. The CSP programming model can be synthesized to different levels, not only used for hardware circuit synthesis: software models (C, ML), intermediate μCode, RTL state level, and finally VHDL. A common source for both hardware and software implementation with identical functional behaviour is used. An extended case study of a communication protocol used in high-density sensoractuator networks should demonstrate the design of a SoC for a robot actuator. The communication protocol is suited for highdensity intraand interchip networks.