Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18�� m CMOS technology and uses 3.3V power supply. The paper implements a 10 bit 50MSPS pipelined ADC using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion and compares them with respect to Area, Speed. Power and Linearity. The paper concludes by stating that 2bits/stage is optimum for a pipelined ADC and to reduce design complexity we can go up to 3 bits/stage. HE rapidly growing electronics has resulted in digital revolution with telephony switching systems in 1970's and continued with digital audio in 1980's and digital video in 1990's. This is expected to prevail in the present multimedia era and even can influence in future systems. Since all electrical signals in nature are analog and since most signal processing is done in the digital domain therefore, A/D and D/A converters have become a necessity. Successive approximation ADC makes single bit decision at a time while flash ADC makes all bit decisions in a single go. Successive approximation ADC is slow and occupies less area while flash ADCs are faster but area increases exponentially with bit length.

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