Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

FinFET technology is prone to suffer from line edge roughness (LER)-based VT variation with scaling. It also lacks a simple implementation of multiple VT technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical simulations that EDFinFET reduces overall VT variability with an 80% reduction in LER-based variability in comparison with FinFETs. We present dynamic threshold MOS (DTMOS) configuration of EDFinFET using the available body terminal to individual transistors. The DTMOS configuration reduces LER-based variability by 90% and overall variability by 59%. It also has excellent subthreshold slope (SS) and gives 43% higher ION compared with FinFETs. Meanwhile, EDFinFET shows poorer SS and lower ION than FinFET due to single gate control. However, it is capable of multiple VT, which leads to circuit level power optimization.

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