A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

High-speed medium-resolution ADCs are widely utilized in high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-VT low-power (LP) CMOS processes making the design of high-speed ADCs challenging. Time-Interleaved (TI) Successive-Approximation-Register-based (SAR) ADCs[1] are ideally suited to these applications due to their highly scalable architecture and due to the steady improvement in matching and density of Metal-Finger Capacitors (MFC). This paper presents a TI C-2C SAR ADC that achieves high performance by using: 1) a small-area C-2C SAR architecture with low input capacitance; 2) high-speed boosted switches to overcome high device threshold; 3) background comparator offset calibration and radix calibration; and 4) redundant-ADC-based gain, offset and timing calibration to reduce TI errors.