Modeling and synthesis of quality-energy optimal approximate adders
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Ku He | Andreas Gerstlauer | Michael Orshansky | Jin Miao | A. Gerstlauer | M. Orshansky | Jin Miao | Ku He
[1] Naresh R. Shanbhag,et al. Soft digital signal processing , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[2] Shih-Lien Lu. Speeding Up Processing with Approximation Circuits , 2004, Computer.
[3] Kang G. Shin,et al. Real-time dynamic voltage scaling for low-power embedded operating systems , 2001, SOSP.
[4] Anantha Chandrakasan,et al. Approximate Signal Processing , 1997, J. VLSI Signal Process..
[5] Braden J. Phillips,et al. Arithmetic Data Value Speculation , 2005, Asia-Pacific Computer Systems Architecture Conference.
[6] A. Chandrakasan,et al. A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization , 1999, IEEE Journal of Solid-State Circuits.
[7] C. Hu,et al. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .
[8] Zhi-Hui Kong,et al. Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[9] Naresh R. Shanbhag,et al. Low-power filtering via adaptive error-cancellation , 2003, IEEE Trans. Signal Process..
[10] A. P. Chandrakasan,et al. Energy efficient filtering using adaptive precision and variable voltage , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).
[11] Anantha Chandrakasan,et al. Transistor sizing issues and tool for multi-threshold CMOS technology , 1997, DAC.
[12] M. Sarrafzadeh,et al. Activity-driven clock design for low power circuits , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[13] Kaushik Roy,et al. IMPACT: IMPrecise adders for low-power approximate computing , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.
[14] Robert K. Brayton,et al. ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions , 1993, 30th ACM/IEEE Design Automation Conference.
[15] Paolo Ienne,et al. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.
[16] Ahmed M. Eltawil,et al. Low-Power Multimedia System Design by Aggressive Voltage Scaling , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[17] Krishna V. Palem,et al. An approach to energy-error tradeoffs in approximate ripple carry adders , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.
[18] B. M. Gordon,et al. Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.
[19] Gang Wang,et al. Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.
[20] Lingamneni Avinash,et al. Energy parsimonious circuit design through probabilistic pruning , 2011, 2011 Design, Automation & Test in Europe.
[21] Massoud Pedram,et al. Clock-gating and its application to low power design of sequential circuits , 2000 .