Area-efficient mixed-radix variable-length FFT processor

: This paper presents a mixed-radix multipath delay feedback (MDF) FFT processor with variable-length. In order to minimize the number of occupied multipliers while supporting more fl exible FFT length, a 4-parallel radix-2 3 mixed radix-2 / 3 / 4 architecture is adopted. In order to further optimize the area and power consumption, we make e ff orts in constant multiplier design, twiddle factor generation and butter fl y units multiplexing. CSD multiplier is adopted to realize the constant factor multi-plication in radix-2 3 and radix-3 butter fl y. Only one CORDIC, several adders and multipliers are occupied to achieve the 4-parallel twiddle factor generation. A radix-2 / 3 / 4 multiplexing butter fl y unit with simple control logic is also designed. The design is synthesized with 65 nm CMOS technology. Compared with previous works, the proposed design shows advantages in terms of area, power consumption, and processing latency.