High-Level Design Verification Techniques for Hardware-Software Codesign Systems

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.