A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities

A hardware based, fully functional, stable 2.4 Mb L1 and L2 Cache compatible 6T embedded SRAM is demonstrated. Measured results show an operating range of -40degC to 120degC, speed of 6.5 GHz and 3.8 GHz for L1-Cache cells and L2-Cache cells, respectively, at 1 V and 25degC, with high yield. The key features include multi-setting programmable clock block, separate read/write margin circuitry, low noise dynamic decoders, bit select circuitry supported by newly developed fast Monte Carlo technique useful for improved cell stability, writeability, and enhanced yield. A novel Burst Mode feature allows defect analysis at high frequency while using slow tester speeds.