High-quality sub-function construction in functional decomposition based on information relationship measures

Functional decomposition seems to be the most effective circuit synthesis approach for look-up table (LUT) FPGAs, (C)PLDs and complex gates. In the functional decomposition that targets LUT FPGAs, the circuit is constructed by recursively decomposing a given function and its sub-functions until each of the resulting sub-functions can be directly implemented with a LUT. The choice of sub-functions constructed in this process decides the quality of the resulting multi-level circuit expressed in terms of the logic block count and speed. In this paper, we propose a new effective and efficient method for the sub-function construction, and we consider its application in our circuit synthesis tool that targets LUT-based FPGAs. The method is based on the information relationship measures. The experimental results demonstrate that the proposed approach leads to extremely fast and very small circuits.

[1]  Sze-Tsen Hu.  ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .

[2]  Lech Józwiak,et al.  Information relationships and measures in application to logic design , 1999, Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329).

[3]  Lech Józwiak,et al.  High-quality FPGA designs through functional decomposition with sub-function input support selection based on information relationship measures , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[4]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[5]  Wen-Zen Shen,et al.  Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping , 1995, 32nd Design Automation Conference.

[6]  Mariusz Rawski,et al.  The influence of the number of values in sub-functions on the effectiveness and efficiency of the functional decomposition , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

[7]  Shih-Chieh Chang,et al.  Technology Mapping via Transformations of Function Graphs , 1992, ICCD.

[8]  Marek Perkowski,et al.  A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping , 1992 .

[9]  H. Allen Curtis.  A Generalized Tree Circuit , 1961, JACM.

[10]  Ulf Schlichtmann,et al.  Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs , 1999, TODE.

[11]  Richard M. Karp,et al.  Minimization Over Boolean Graphs , 1962, IBM J. Res. Dev..

[12]  J. Hartmanis,et al.  Algebraic Structure Theory Of Sequential Machines , 1966 .

[13]  Lech Jóźwiak,et al.  General Decomposition and Its Use in Digital Circuit Synthesis , 1995 .

[14]  Hiroshi Sawada,et al.  Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization , 1995, ICCAD.

[15]  Lech Józwiak,et al.  Information relationships and measures: an analysis apparatus for efficient information system synthesis , 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).

[16]  Claude E. Shannon,et al.  The synthesis of two-terminal switching circuits , 1949, Bell Syst. Tech. J..

[17]  J. Hartmanis.  Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics) , 1966 .