A 200mhz 16mbit Synchronous Dram With Block Access Mode
暂无分享，去创建一个
Toshio Yamada | Atsushi Fujiwara | Hirohito Kikukawa | Shozo Okada | Masashi Agata | K. Matsuyama | Shunichi Iwanari | M. Fukumoto | T. Fujita | M. Fukumoto | S. Okada | H. Kikukawa | T. Yamada | M. Agata | S. Iwanari | A. Fujiwara | K. Matsuyama | T. Fujita
[1] Hiroyuki Yamauchi,et al. A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's , 1993 .
[2] T. Obara,et al. 250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture , 1993, Symposium 1993 on VLSI Circuits.