Interconnect pipelining in a throughput-intensive FPGA architecture

Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, cirðcuits inherently utilize latches. Inside the synthesized structures they are used for signal skewing, and on the interconnects to guarðantee the correct arrival times at the inputs. Recently, we proposed a novel high-throughput FPGA architecture based on the wave-steering design principle to handle throughput-intensive applicaðtions. Previously our work was focussed mainly on the Logic Block (LB) design. In this paper we discuss a pipelined interconðnect scheme to support the strict timing requirements that is necesðsitated by the wave-steered design style. We characterize designs that best fit the new architecture and show that as technology scales down towards deep submicron (DSM), this FPGA fabric shows an increasing throughput performance.