A tolerant JPEG-LS image compressor foreseeing COTS FPGA implementation

Study of a compact solution for onboard tolerant image compression.Low-complexity JPEG-LS image compression standard allows considering medium-size flash or antifuse FPGAs for future use in small satellites.Widespread TMR and Hamming code plus scrubbing selected to mitigate error accumulation, considering a LEO space radiation environment.Evaluation of the effectiveness of the mitigation strategy by using a simulation-based susceptibility analysis method.Results pointed out two orders-of-magnitude reduction in the susceptibility estimate and enough room for improvements. A compact solution for onboard tolerant image compression is studied and the effectiveness of the soft-error mitigation strategy is evaluated by using a simulation-based susceptibility analysis method. The low complexity JPEG-LS compression algorithm allows considering medium-size flash or antifuse COTS FPGAs as a target for future use in small satellites. Fault mitigation methods, like Triple Modular Redundancy and Hamming code, with scrubbing to mitigate residual error accumulation, were selected taking into account operation in LEO space missions. The results point out the viability of implementing a tolerant image compression system in a single device with two orders-of-magnitude reduction in the susceptibility estimate based on a non-tolerant reference VHDL code. The effectiveness of the mitigation strategy, the injection model accuracy and possible improvements are discussed herein. Display Omitted

[1]  John Wall,et al.  The past, present and future of EEE components for space application: COTS ‐ the next generation , 1998 .

[2]  L. Sterpone,et al.  Analysis of SET propagation in flash-based FPGAs by means of electrical pulse injection , 2009, 2009 European Conference on Radiation and Its Effects on Components and Systems.

[3]  Roberto d'Amore,et al.  Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation , 2012, IET Comput. Digit. Tech..

[4]  Marty R. Shaneyfelt,et al.  Use of COTS microelectronics in radiation environments , 1999 .

[5]  Guillermo Sapiro,et al.  The LOCO-I lossless image compression algorithm: principles and standardization into JPEG-LS , 2000, IEEE Trans. Image Process..

[6]  Luigi Carro,et al.  On the use of VHDL simulation and emulation to derive error rates , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[7]  S. Rezgui,et al.  Comprehensive SEE characterization of 0.13µm flash-based FPGAs by heavy ion beam test , 2007, 2007 9th European Conference on Radiation and Its Effects on Components and Systems.

[8]  Roberto d'Amore,et al.  A low complexity image compression solution for onboard space applications , 2010, SBCCI '10.

[9]  Massimo Violante,et al.  New techniques for accelerating fault injection in VHDL descriptions , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

[10]  Thomas Polzer,et al.  An infrastructure for accurate characterization of single-event transients in digital circuits☆ , 2013, Microprocess. Microsystems.

[11]  Pedro Reviriego,et al.  Fault tolerant FIR filters using hamming codes , 2009, 2009 European Conference on Radiation and Its Effects on Components and Systems.

[12]  S. Rezgui,et al.  New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA3P , 2008, 2008 IEEE Aerospace Conference.

[13]  S Schulz,et al.  Smart behavioral netlist simulation for SEU protection verification , 2008, 2008 European Conference on Radiation and Its Effects on Components and Systems.

[14]  Martin E. Fraeman,et al.  Harsh environments : space radiation environment, effects, and mitigation , 2008 .

[15]  E. G. Stassinopoulos,et al.  The space radiation environment for electronics , 1988, Proc. IEEE.

[16]  R. Chipana,et al.  TID in Flash-Based FPGA: Power Supply-Current Rise and Logic Function Mapping Effects in Propagation-Delay Degradation , 2011, IEEE Transactions on Nuclear Science.

[17]  Massimo Violante,et al.  An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits , 2002, J. Electron. Test..

[18]  S. Kayali Utilization of COTS electronics in space application, reliability challenges and reality , 2002 .

[19]  Robert Ecoffet,et al.  In-flight observations of the radiation environment and its effects on devices in the SAC-C polar orbit , 2002 .

[20]  Stephen LaLumondiere,et al.  A single event latchup suppression technique for COTS CMOS ICs , 2003 .

[21]  Heinrich Theodor Vierhaus,et al.  Simulated fault injections and their acceleration in SystemC , 2008, Microprocess. Microsystems.