Exploring pausible clocking based GALS design for 40-nm system integration
暂无分享,去创建一个
Christoph Heer | Xin Fan | Eckhard Grass | Milos Krstic | Birgit Sanders | E. Grass | M. Krstic | Xin Fan | Birgit Sanders | C. Heer
[1] Wolfgang Fichtner,et al. Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).
[2] Edith Beigné,et al. Design and Implementation of a GALS Adapter for ANoC Based Architectures , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.
[3] H. Lhermet,et al. An Asynchronous Power Aware and Adaptive NoC Based Circuit , 2009, IEEE Journal of Solid-State Circuits.
[4] Kenneth Y. Yun,et al. Pausible clocking: a first step toward heterogeneous systems , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.
[5] Xin Fan,et al. Analysis and optimization of pausible clocking based GALS design , 2009, 2009 IEEE International Conference on Computer Design.
[6] Xin Fan,et al. A GALS FFT processor with clock modulation for low-EMI applications , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.
[7] Johnny Öberg,et al. Lowering power consumption in clock by using globally asynchronous locally synchronous design style , 1999, DAC '99.
[8] Wolfgang Fichtner,et al. On the GALS design methodology of ETH Zurich , 2003 .
[9] Daniel Marcos Chapiro,et al. Globally-asynchronous locally-synchronous systems , 1985 .
[10] Luciano Lavagno,et al. Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .