A unified execution model for multiple computation models of streaming applications on a composable MPSoC

In this paper we propose a unified model of execution that aims to fill the abstraction level gap between the primitives of models of computation and the ones of an MPSoC. This model targets a composable MPSoC platform and supports the sequential, Kahn process networks, and dataflow models. Our model comprises of (1) execution operations implementing the primitives in the models of computation, and (2) a time model of execution of streaming applications on a composable platform. We implement these models of computation with the model of execution, and discuss the trade-offs involved. Case studies on an FPGA prototype of the composable MPSoC demonstrate how the model of execution actually works on a real platform. Furthermore they indicate that multiple applications modeled in KPN and dataflow run composably on the platform.

[1]  Axel Jantsch,et al.  System modeling and transformational design refinement in ForSyDe [formal system design] , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  E.A. Lee,et al.  A comparison of synchronous and cycle-static dataflow , 1995, Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers.

[3]  Alexandru Turjan,et al.  Translating affine nested-loop programs to process networks , 2004, CASES '04.

[4]  Todor Stefanov,et al.  pn: A Tool for Improved Derivation of Process Networks , 2007, EURASIP J. Embed. Syst..

[5]  E. Rijpkema,et al.  Compaan: deriving process networks from Matlab for embedded signal processing architectures , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).

[6]  Sander Stuijk,et al.  SDF^3: SDF For Free , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[7]  Edward A. Lee,et al.  Timed multitasking for real-time embedded software , 2003 .

[8]  Marco Platzner,et al.  Efficient execution of process networks on a reconfigurable hardware virtual machine , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[9]  Edward A. Lee,et al.  Execution Strategies for PTIDES, a Programming Model for Distributed Embedded Systems , 2009, 2009 15th IEEE Real-Time and Embedded Technology and Applications Symposium.

[10]  Sander Stuijk,et al.  Analyzing concurrency in streaming applications , 2008, J. Syst. Archit..

[11]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[12]  Gerard J. M. Smit,et al.  Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[13]  Stamatis Vassiliadis,et al.  Architectural Elements of Integrated Micro-Sensors for Distributed Sensor Networks , 2007 .

[14]  Hermann Kopetz,et al.  Real-time systems , 2018, CSC '73.

[15]  Rainer Leupers,et al.  Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[16]  Kees G. W. Goossens,et al.  C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems , 2002, Des. Autom. Embed. Syst..

[17]  Johan Eker,et al.  A STRUCTURED DESCRIPTION OF DATAFLOW ACTORS AND ITS APPLICATION , 2003 .

[18]  Stamatis Vassiliadis,et al.  Customizing Reconfigurable On-Chip Crossbar Scheduler , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

[19]  Kees G. W. Goossens,et al.  The aethereal network on chip after ten years: Goals, evolution, lessons, and future , 2010, Design Automation Conference.

[20]  Grant Martin,et al.  Overview of the MPSoC design challenge , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[21]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[22]  Lothar Thiele,et al.  Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs , 2009, 2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia.

[23]  Pedro P. Carballo,et al.  CASSE: a system-level modeling and design-space exploration tool for multiprocessor systems-on-chip , 2004 .

[24]  Carlo Rossi,et al.  Giotto a time-triggered language for embedded programming , 2011 .

[25]  Edward A. Lee,et al.  Dataflow process networks , 2001 .

[26]  J.,et al.  Composability and Predictability for Independent Application Development , Verification and Execution , 2010 .

[27]  Edward A. Lee,et al.  A framework for comparing models of computation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Frédéric Pétrot,et al.  Platform-based design from parallel C specifications , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Kees G. W. Goossens,et al.  Design and implementation of an operating system for composable processor sharing , 2011, Microprocess. Microsystems.

[30]  Kees G. W. Goossens,et al.  Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis , 2009, IET Comput. Digit. Tech..

[31]  Yajun Ha,et al.  Analyzing composability of applications on MPSoC platforms , 2008, J. Syst. Archit..

[32]  Edward A. Lee,et al.  Concurrent models of computation for embedded software , 2005 .

[33]  Alexandru Turjan,et al.  System design using Khan process networks: the Compaan/Laura approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[34]  Orlando Moreira,et al.  Multiprocessor resource allocation for hard-real-time streaming with a dynamic job-mix , 2005, 11th IEEE Real Time and Embedded Technology and Applications Symposium.

[35]  Kees G. W. Goossens,et al.  Architectures and modeling of predictable memory controllers for improved system integration , 2011, 2011 Design, Automation & Test in Europe.

[36]  Stamatis Vassiliadis,et al.  Systematic Customization of On-Chip Crossbar Interconnects , 2007, ARC.

[37]  Edward A. Lee,et al.  Temporal isolation on multiprocessing architectures , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[38]  Ahmed Amine Jerraya,et al.  Programming models and HW-SW interfaces abstraction for multi-processor SoC , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[39]  Maarten Wiggers,et al.  Efficient buffer capacity and scheduler setting computation for soft real-time stream processing applications , 2007, SCOPES '07.

[40]  S. Stuijk.  Predictable mapping of streaming applications on multiprocessors , 2007 .

[41]  Kees G. W. Goossens,et al.  CoMPSoC: A template for composable and predictable multi-processor system on chips , 2009, TODE.

[42]  Ed F. Deprettere,et al.  Laura: Leiden Architecture Research and Exploration Tool , 2003, FPL.

[43]  Kees G. W. Goossens,et al.  Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms , 2012, Map2MPSoC/SCOPES.

[44]  Ahmed Amine Jerraya,et al.  Multiprocessor System-on-Chip (MPSoC) Technology , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[45]  Kees G. W. Goossens,et al.  Composability and Predictability for Independent Application Development, Verification, and Execution , 2011, Multiprocessor System-on-Chip.

[46]  Thomas A. Henzinger,et al.  Event-Driven Programming with Logical Execution Times , 2004, HSCC.