A reconfigurable SIMD architecture on-chip

This project targets the problems with design and implementation of Single Instruction Multiple Data (SIMD) architectures in System-on-Chip (SoC), with the goal to construct a reconfigurable framew ...

[1]  John R. Nickolls,et al.  The design of the MasPar MP-1: a cost effective massively parallel computer , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.

[2]  Ulf Blixt,et al.  Konstruktion av mjuk CPU i VHDL , 2004 .

[3]  Yoshihiro Fujita,et al.  A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM , 1994, IEEE J. Solid State Circuits.

[4]  Elias S. Manolakos,et al.  Parallel computation of higher order moments on the MasPar-1 machine , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[5]  Huy Nguyen,et al.  AltiVec/sup TM/: bringing vector technology to the PowerPC/sup TM/ processor family , 1999, 1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305).

[6]  Vladimir M. Pentkovski,et al.  Implementing Streaming SIMD Extensions on the Pentium III Processor , 2000, IEEE Micro.

[7]  Fred Weber,et al.  AMD 3DNow! technology: architecture and implementations , 1999, IEEE Micro.

[8]  Shin'ichiro Okazaki,et al.  A 3.84 gips integrated memory array processor , 1996, Syst. Comput. Jpn..

[9]  Fadi J. Kurdahi,et al.  The MorphoSys dynamically reconfigurable system-on-chip , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[10]  Mikael Taveniku,et al.  A reconfigurable SIMD computer for artificial neural networks , 1995 .

[11]  Stephen A. Dyer,et al.  Digital signal processing , 2018, 8th International Multitopic Conference, 2004. Proceedings of INMIC 2004..

[12]  Eberhard Zehendner Simulating systolic arrays on MasPar machines , 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).