A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template

As modern areas of application for coarse-grained reconfigurable systems digital signal processing, multimedia in embedded devices, and wireless communication can be mentioned among others. These fields include different algorithms with varying complexity and speed requirements. In this paper a new highly parameterizable coarse-grained reconfigurable architecture called weakly programmable processor array is discussed. It consists of several weakly programmable processing elements with a VLIW (Very Large Instruction Word) architecture which are connected with the help of dynamically reconfigurable interconnect modules.

[1]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[2]  Soo-Mook Moon,et al.  Generalized Multiway Branch Unit for VLIW Microprocessors , 1995, IEEE Trans. Parallel Distributed Syst..

[3]  André DeHon,et al.  Reconfigurable architectures for general-purpose computing , 1996 .

[4]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2003, The Journal of Supercomputing.

[5]  Malgorzata Marek-Sadowska,et al.  FPGA interconnect planning , 2002, SLIP '02.

[6]  Bernard Pottier,et al.  Co-Design of Massively Parallel Embedded Processor Architectures , 2005, ReCoSoC.

[7]  Hideharu Amano,et al.  RoMultiC: fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[8]  Wayne Luk,et al.  Reconfigurable computing: architectures and design methods , 2005 .