A digital signal processor (DSP) is described which achieves high processing efficiency by executing concurrently four functions in every processor cycle: instruction prefetching from a dedicated instruction memory and generation of an effective operand, access to a single-port data memory and transfer of a data word over a common data bus, arithmetic/logic-unit (ALU) operation, and multiplication. Instructions have a single format and contain an operand, index control bits, and two independent operation codes called “transfer” code and “compute” code. The first code specifies the transfer of a data word over the common data bus, e.g., from data memory to a local register. The second determines an operation of the ALU on the contents of local registers. A fast free-running multiplier operates in parallel with the ALU and delivers a product in every cycle with a pipeline delay of two cycles. The architecture allows transversal-filter operations to be performed with one multiplication and ALU operation in every cycle. This is accomplished by a novel interleaving technique called ZIP-ing. The efficiency of the processor is demonstrated by programming examples.
[1]
Abraham Peled,et al.
A Microprocessor for Signal Processing, the RSP
,
1982,
IBM J. Res. Dev..
[2]
Khen-Sang Tan,et al.
A chip set for audio frequency digital signal processing
,
1982,
ICASSP.
[3]
I. I. Eldumiati,et al.
Digital signal processor: Architecture and performance
,
1981,
The Bell System Technical Journal.
[4]
Gottfried Ungerboeck,et al.
The SP16 signal processor
,
1984,
ICASSP.
[5]
T. Inaba,et al.
A 23K gate CMOS DSP with 100ns multiplication
,
1983,
1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[6]
M. Townsend,et al.
An NMOS Microprocessor for Analog Signal Processing
,
1980
.
[7]
S. Magar,et al.
A microcomputer with digital signal processing capability
,
1982,
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.