Circuit optimization via adjoint Lagrangians

The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper, we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmented-Lagrangian-based optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program. The adjoint Lagrangian formulation has been implemented in the JiffyTune tool which optimizes delay, area, slew (transition time) and power measurements by adjusting transistor widths and wire sizes. Speedups of over 35x have been realized in the gradient computation procedure by using the adjoint Lagrangian formulation, leading to speedups of up to 2.5x in the overall optimization procedure. Perhaps more importantly, these speedups have rendered feasible the tuning of large circuits. A circuit with 6,900 transistors was optimized in under two hours of CPU time.

[1]  Weitong Chuang,et al.  Power vs. delay in gate sizing: conflicting objectives? , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[2]  Ronald A. Rohrer,et al.  Sensitivity computation in piecewise approximate circuit simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  M. J. D. Powell,et al.  A method for nonlinear constraints in minimization problems , 1969 .

[4]  M. Hestenes Multiplier and gradient methods , 1969 .

[5]  Robert K. Brayton,et al.  The Sparse Tableau Approach to Network Analysis and Design , 1971 .

[6]  Robert K. Brayton,et al.  Computation of delay time sensitivities for use in time domain optimization , 1975 .

[7]  Ronald A. Rohrer,et al.  Piecewise approximate circuit simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Ronald A. Rohrer,et al.  SPECS simulation validation with efficient transient sensitivity computation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[9]  P. Toint,et al.  Global convergence of a class of trust region algorithms for optimization with simple bounds , 1988 .

[10]  Robert K. Brayton,et al.  Sensitivity and optimization , 1980 .

[11]  Dimitri P. Bertsekas,et al.  Constrained Optimization and Lagrange Multiplier Methods , 1982 .

[12]  Alberto L. Sangiovanni-Vincentelli,et al.  DELIGHT.SPICE: an optimization-based system for the design of integrated circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  L. Pileggi,et al.  A sequential quadratic programming approach to concurrent gate and wire sizing , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[14]  Nicholas I. M. Gould,et al.  Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A) , 1992 .

[15]  Chandramouli Visweswariah,et al.  Incremental Event-Driven Simulation of Digital FET Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[16]  Alberto Sangiovanni-Vincentelli,et al.  SPICE: An optimization-based system for the design of integrated circuits , 1988, ICCAD 1988.

[17]  M.D. Matson,et al.  Macromodeling and Optimization of Digital MOS VLSI Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Sachin S. Sapatnekar,et al.  Optimal design of macrocells for low power and high speed , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[20]  Tuyen Van Nguyen Transient sensitivity computation and applications , 1991 .

[21]  Andrew R. Conn,et al.  Optimization of custom MOS circuits by transistor sizing , 1996, ICCAD 1996.

[22]  R. Rohrer The Generalized Adjoint Network and Network Sensitivities , 1969 .

[23]  Andrew R. Conn,et al.  Two-Step Algorithms for Nonlinear Optimization with Structured Applications , 1999, SIAM J. Optim..

[24]  A.L. Sangiovanni-Vincentelli,et al.  A survey of optimization techniques for integrated-circuit design , 1981, Proceedings of the IEEE.

[25]  Alberto L. Sangiovanni-Vincentelli,et al.  ECSTASY: a new environment for IC design optimization , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.