Quilt Packaging: High-Density, High-Speed Interchip Communications

ldquoQuilt packagingrdquo (QP), a new superconnect paradigm for interchip communication, is presented. QP uses conducting nodules that protrude from the vertical facets of integrated circuits to effect a dense, fast, and reduced-power method of interfacing multiple die together within a package or on a multichip module. The concept of QP is presented along with a discussion of advantages over traditional system-on-chip and other system-in-package technologies. A process flow and results of chip fabrication are detailed. Simulations show expected signal propagation between adjacent die of greater than 200 GHz, and measurements of interconnected chips confirming low losses and resonance-free operation to at least 40 GHz have been achieved.

[1]  H. Bernhard Pogge.  The next chip challenge: effective methods for viable mixed technology SoCs , 2002, DAC '02.

[2]  Takayasu Sakurai.  Superconnect Technology(Special Issue on Integrated Systems with New Concepts) , 2001 .

[3]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .

[4]  S. Sommerfeldt,et al.  Packaging of microwave integrated circuits operating beyond 100 GHz , 2002, Proceedings. IEEE Lester Eastman Conference on High Performance Devices.

[5]  Frank Ansorge,et al.  Innovative packaging concepts for ultra thin integrated circuits , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[6]  D. DiMarco,et al.  A 16 GB/s, 0.18 /spl mu/m cache tile for integrated L2 caches from 256 KB to 2 MB , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[7]  Rajiv V. Joshi,et al.  Three dimensional CMOS devices and integrated circuits , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[8]  R. Hopkins,et al.  Proximity communication , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[9]  Takayasu SAKURAI†a.  Superconnect Technology , 2001 .

[10]  Paul D. Franzon,et al.  3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver , 2006, IEEE Journal of Solid-State Circuits.

[11]  Robert B. Bass,et al.  Beam lead quartz chips for superconducting millimeter-wave circuits , 2003, SPIE Astronomical Telescopes + Instrumentation.

[12]  J. F. McDonald,et al.  The trials of wafer-scale integration: Although major technical problems have been overcome since WSI was first tried in the 1960s, commercial companies can't yet make it fly , 1984, IEEE Spectrum.

[13]  S. Datta,et al.  Silicon nano-transistors and breaking the 10 nm physical gate length barrier , 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

[14]  S. Das,et al.  Fabrication technologies for three-dimensional integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.

[15]  Qing Liu,et al.  Quilt packaging: a new paradigm for interchip communication , 2005, 2005 7th Electronic Packaging Technology Conference.

[16]  M.J. Kobrinsky,et al.  Comparisons of conventional, 3-D, optical, and RF interconnects for on-chip clock distribution , 2004, IEEE Transactions on Electron Devices.

[17]  T. Sakurai,et al.  A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package , 2006, IEEE Journal of Solid-State Circuits.

[18]  C. Landesberger,et al.  New dicing and thinning concept improves mechanical reliability of ultra thin silicon , 2001, Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562).

[19]  Henning Braunisch,et al.  Electrical performance of bumpless build-up layer packaging , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[20]  Peter M. Kogge,et al.  PIM architectures to support petaflops level computation in the HTMT machine , 1999, Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650).

[21]  Anna W. Topol,et al.  Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication , 2002, Digest. International Electron Devices Meeting,.

[22]  David Wentzlaff,et al.  Energy characterization of a tiled architecture processor with on-chip networks , 2003, ISLPED '03.