A novel method of analytically extracting model parameters for stacked transformers

SUMMARY An accurate compact model for stacked transformers is proposed. The parasitics between the primary metal coils and the substrate are taken into consideration. The model parameters can be analytically extracted from open-loaded S-parameters measured from two-port test structures. The modeling methodology renders excellent agreement with the data from both simulation and measurement over the frequency range of 0.1–20 GHz for a monolithic stacked transformer manufactured in 0.18-µm Radio frequency Complementary Metal Oxide Semiconductor (RF CMOS) technology. Copyright © 2015 John Wiley & Sons, Ltd.

[1]  Yo-Sheng Lin,et al.  High-Coupling and Ultra-Low-Loss Interlaced Stacked Transformers for 60-100 GHz CMOS RFIC Applications , 2007 .

[2]  Kiat Seng Yeo,et al.  Fully Symmetrical Monolithic Transformer (True 1 : 1) for Silicon RFIC , 2008, IEEE Transactions on Microwave Theory and Techniques.

[3]  A. Weisshaar,et al.  A new compact model for monolithic transformers in silicon-based RFICs , 2005, IEEE Microwave and Wireless Components Letters.

[4]  T. Biondi,et al.  Analysis and modeling of layout scaling in silicon integrated stacked transformers , 2006, IEEE Transactions on Microwave Theory and Techniques.

[5]  Hao Yu,et al.  A new model of stacked transformers considering skin and substrate effects , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

[6]  J. Burghartz,et al.  Substrate effects in monolithic RF transformers on silicon , 2002 .

[7]  Zhiping Yu,et al.  A Broadband Model Over 1–220 GHz for GSG Pad Structures in RF CMOS , 2014, IEEE Electron Device Letters.

[8]  Behzad Razavi,et al.  Stacked inductors and transformers in CMOS technology , 2001 .

[9]  Jean-Baptiste Begueret,et al.  Modeling of integrated monolithic transformers for silicon RF IC , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[10]  Jian Chen,et al.  A Compact Fully Integrated High-Efficiency 5GHz Stacked Class-E PA in 65nm CMOS Based on Transformer-Based Charging Acceleration , 2012, 2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[11]  Chuan Wang,et al.  A Wideband Predictive “Double-$\pi$ ” Equivalent-Circuit Model for On-Chip Spiral Inductors , 2009, IEEE Transactions on Electron Devices.

[12]  Tao Liu,et al.  Scalable Compact Circuit Model for Differential Spiral Transformers in CMOS RFICs , 2006, IEEE Transactions on Electron Devices.

[13]  J.R. Long,et al.  A 1.2 V Reactive-Feedback 3.1–10.6 GHz Low-Noise Amplifier in 0.13 $\mu{\hbox {m}}$ CMOS , 2007, IEEE Journal of Solid-State Circuits.

[14]  Liu Jun,et al.  A novel compact model for on-chip stacked transformers in RF-CMOS technology , 2013 .

[15]  Shyh-Jong Chung,et al.  Accurate Systematic Model-Parameter Extraction for On-Chip Spiral Inductors , 2008, IEEE Transactions on Electron Devices.

[16]  Zuochang Ye,et al.  Broadband compact model for on-chip mm-wave transformers and baluns with emphasis on capacitive coupling effects , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[17]  Chuan Wang,et al.  A new approach to parameter extraction for on-chip symmetric transformers , 2009, 2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

[18]  R. Castello,et al.  An innovative modelization of loss mechanism in silicon integrated inductors , 1999 .