Analysis of simultaneous switching noise

With increasing system speed and I/O-count a noise phenomenon known as /spl Delta/I-Noise becomes more important and emerges as a limiting factor for reliable high speed chip-to-chip interconnections. Using a simplified model for CMOS drivers, the main effects of /spl Delta/I-Noise are investigated analytically and the impact of the model's key parameters on the noise magnitudes and the driver delay is shown.