A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

Abstract Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the best compromise between these approaches, we have developed the OORBIT tool (Offline/Online Relocation of Bitstreams) which accelerates the relocation time considerably. The methodology consists, firstly, in an offline bitstream modification phase which generates relocatable bitstreams including additional relocation data. Afterwards, online relocation is performed by a simple substitution of the initial location data by those calculated offline, corresponding to the target PRR. In this paper, we provide a detailed description of our methodology, emphasizing its interaction with the newest Xilinx Partition PR Design Flow, which results in major changes compared to previous efforts. Finally, a performance comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation more amenable.

[1]  Jürgen Teich,et al.  ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[2]  Barry E. Mullins,et al.  Using Relocatable Bitstreams for Fault Tolerance , 2012, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[3]  Jim Tørresen,et al.  Zero logic overhead integration of partially reconfigurable modules , 2010, SBCCI '10.

[4]  Jürgen Becker,et al.  An FPGA run-time system for dynamical on-demand reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[5]  Jürgen Teich,et al.  A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[6]  Adam Donlin.  Applications, Design Tools and Low Power Issues in FPGA Reconfiguration , 2007 .

[7]  Heiko Kalte,et al.  REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs , 2006, CF '06.

[8]  Jooheung Lee,et al.  An array-based scalable architecture for DCT computations in video coding , 2008, 2008 International Conference on Neural Networks and Signal Processing.

[9]  Ulrich Rückert,et al.  REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[10]  Aravind Dasu,et al.  PRR-PRR Dynamic Relocation , 2009, IEEE Computer Architecture Letters.

[11]  Jean-Didier Legat,et al.  An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications , 2008, EURASIP J. Embed. Syst..

[12]  Ali Akoglu,et al.  Self-configurable architecture for reusable systems with Accelerated Relocation Circuit (SCARS-ARC) , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

[13]  Jooheung Lee,et al.  Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration , 2009, TECS.

[14]  Jim Tørresen,et al.  Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[15]  Mario Porrmann,et al.  Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs , 2007, ERSA.

[16]  Marco D. Santambrogio,et al.  Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Wayne Luk,et al.  Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration , 2007 .

[18]  Alessandro Forin,et al.  Automatic bus macro placement for partially reconfigurable FPGA designs , 2009, FPGA '09.

[19]  Fabrizio Ferrandi,et al.  Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[20]  Phillip H. Jones,et al.  Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[21]  M. Huebner,et al.  Seamless Design Flow for Run-Time Reconfigurable Automotive Systems , 2006 .