Software-Hardware Co-verification for ASIP Design

To increase the efficiency of verification in design of Application Specific Instruction Set Processor(ASIP), a software-hardware co-verification method which combines the verification of ASIP Register Transport Level(RTL) description with the test of ASIP software development tools(assembler, software simulator) is proposed. Test assemble instructions and data are generated according to the test requirement, and the binary codes are produced by the assembler subsequently. The binary codes are input to the hardware simulator and instruction set simulator at same time, and the results of software and hardware simulation are compared automatically. This method can discover errors in ASIP RTL description, the assembler and the instruction set simulator efficiently, increase the coverage of verification, and shorten the verification cycle of ASIP.