Development of silicon module with TSVs and global wiring (L/S=0.8/0.8µm)
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K. Murayama | Masahiro Sunohara | M. Sunohara | K. Murayama | M. Higashi | M. Higashi | A. Shiraishi | Y. Taguchi | M. Shimizu | Y. Taguchi | A. Shiraishi | M. Shimizu
[1] M. Matsuo,et al. Novel low cost integration of through chip interconnection and application to CMOS image sensor , 2006, 56th Electronic Components and Technology Conference 2006.
[2] B. Dang,et al. 3D silicon integration , 2008, 2008 58th Electronic Components and Technology Conference.
[3] Reflowable ISM WLP , 2008, 2008 58th Electronic Components and Technology Conference.
[4] T. Kurihara,et al. A Silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect , 2008, 2008 58th Electronic Components and Technology Conference.
[5] J. Knickerbocker,et al. A CMOS-compatible process for fabricating electrical through-vias in silicon , 2006, 56th Electronic Components and Technology Conference 2006.
[6] K. Najafi,et al. Gold-indium Transient Liquid Phase (TLP) wafer bonding for MEMS vacuum packaging , 2008, 2008 IEEE 21st International Conference on Micro Electro Mechanical Systems.
[7] E. Beyne,et al. Optimizing Au and In micro-bumping for 3D chip stacking , 2008, 2008 58th Electronic Components and Technology Conference.
[8] S. Muthukumar,et al. Fabrication and electrical characterization of 3D vertical interconnects , 2006, 56th Electronic Components and Technology Conference 2006.
[9] Satoru Kuramochi,et al. High-density packaging technologies on silicon substrates , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..
[10] H. Reichl,et al. Through silicon via technology — processes and reliability for wafer-level 3D system integration , 2008, 2008 58th Electronic Components and Technology Conference.