A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes

This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing the layered LDPC decoding schedule, and 2) architecturally, by optimizing register-based memories for IEEE 802.11n/ac LDPC codes and implementing an idle-cycle-free pipelined single-codeword datapath decoder. Register-based memories provide full bandwidth access to read and write all messages of a layer in one clock cycle. Single-codeword processing in the datapath significantly reduces memory overhead compared to other architectures that process multiple codewords to boost throughput at the expense of a larger footprint. The proposed architecture is synthesized in 40 nm CMOS process for IEEE 802.11 n/ac, rate 1/2 LDPC codes. The decoder occupies an area of 0.38 mm2, runs at a frequency of 780 MHz, and achieves a throughput of 4.2 Gbps.

[1]  Joseph R. Cavallaro,et al.  Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[2]  D.J.C. MacKay,et al.  Good error-correcting codes based on very sparse matrices , 1997, Proceedings of IEEE International Symposium on Information Theory.

[3]  Zhongfeng Wang,et al.  Reduced-complexity column-layered decoding and implementation for LDPC codes , 2011, IET Commun..

[4]  H. Kfir,et al.  Parallel versus sequential updating for belief propagation decoding , 2002, cond-mat/0207185.

[5]  Po-Hsun Cheng,et al.  Improvement on a block-serial fully-overlapped QC-LDPC decoder for IEEE 802.11n , 2014, 2014 IEEE International Conference on Consumer Electronics (ICCE).

[6]  Mohammad M. Mansour,et al.  A Turbo-Decoding Message-Passing Algorithm for Sparse Parity-Check Matrix Codes , 2006, IEEE Transactions on Signal Processing.

[7]  Joseph R. Cavallaro,et al.  Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[8]  Philippe Flatresse,et al.  27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[9]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[10]  S. Litsyn,et al.  An efficient message-passing schedule for LDPC decoding , 2004, 2004 23rd IEEE Convention of Electrical and Electronics Engineers in Israel.

[11]  Mohammad M. Mansour,et al.  A 640-Mb/s 2048-bit programmable LDPC decoder chip , 2006, IEEE Journal of Solid-State Circuits.

[12]  Borivoje Nikolic,et al.  LDPC decoder architecture for high-data rate personal-area networks , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[13]  Naresh R. Shanbhag,et al.  Memory-efficient turbo decoder architectures for LDPC codes , 2002, IEEE Workshop on Signal Processing Systems.

[14]  Naresh R. Shanbhag,et al.  High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Roy P. Paily,et al.  High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[17]  Gwan S. Choi,et al.  Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[18]  William Stallings,et al.  Local and Metropolitan Area Networks , 1993 .

[19]  Martin J. Wainwright,et al.  An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors , 2010, IEEE Journal of Solid-State Circuits.

[20]  Ali Chehab,et al.  Interlaced Column-Row Message-Passing Schedule for Decoding LDPC Codes , 2016, 2016 IEEE Global Communications Conference (GLOBECOM).

[21]  Radford M. Neal,et al.  Near Shannon limit performance of low density parity check codes , 1996 .

[22]  Juntan Zhang,et al.  Shuffled belief propagation decoding , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[23]  Luca Fanucci,et al.  A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes , 2007, IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference.