Analysis and optimization of Active Power and Delay of 10T Full Adder using Power Gating Technique at 45 nm Technology

An overview of performance analysis and comparison between various parameters of a low power high speed 10T full adder has been presented here. This paper shows comparative study of advancement over active power, leakage current and delay with power supply of (0.7v) .We have achieved reduction in active power consumption of 39.20 nW and propagation delay of 10.51 ns, which makes this circuit highly energy efficient and optimization can be achieved between power and delay. In this circuit we have reduced leakage current of 18.21 nA for power supply of 0.5v to 0.9v. Signification of these designs is substance by the simulation results obtained from cadence virtuoso tool at different technologies.

[1]  Rohit Maurya,et al.  A Study and Analysis of High Speed Adders in Power-Constrained Environment , 2012 .

[2]  Mohamed I. Elmasry,et al.  Design and optimization of multithreshold CMOS (MTCMOS) circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Haranath Kar,et al.  Multi-threshold CMOS design for low power digital circuits , 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

[4]  Magdy A. Bayoumi,et al.  Performance evaluation of 1-bit CMOS adder cells , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[5]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .

[6]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[7]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[8]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[9]  Sudarshan Tiwari,et al.  Comparative Performance Analysis of XOR- XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design , 2012, VLSIC 2012.

[10]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[11]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[12]  Earl E. Swartzlander,et al.  Low Power Arithmetic Components , 1996 .

[13]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..