Skewed Flip-Flop and Mixed-$V_{t}$ Gates for Minimizing Leakage in Sequential Circuits

Mixed V t has been widely used to control leakage without affecting circuit performance. However, existing approaches only target combinational circuits, even though sequential elements such as flip-flops contribute an appreciable proportion of the total leakage. Applying high V t to ordinary flip-flops would reduce the number of combinational gates that can be assigned to high V t, because any timing slacks would be absorbed by the increased setup guard time and propagation delay of the high-V t flip-flops. A skewed flip-flop (SFF) can be constructed by replacing a subset of transistors in a conventional flip-flop with low-leakage devices, such as large- L gate transistors. In terms of leakage and delay, SFFs exhibit very skewed characteristic, which depends on the transistors that are replaced. Our algorithm selectively substitutes SFFs for conventional flip-flops in sequential circuits so as to reduce the leakage while continuing to satisfy the timing constraint. When combined with the mixed-V t combinational circuits, this achieves an average leakage saving of 15% compared to mixed V t alone. The leakage of the flip-flops themselves is cut by 25% on average.