Tapered-Vth Approach for Energy-Efficient

In this paper, "tapered-Vth" buffers are explored as an approach to significantly improve the energy efficiency of tra- ditional CMOS buffers. In this approach, the transistor threshold voltage is progressively increased throughout the buffer stages, in addition to the traditional transistor tapered sizing. Analysis shows that tapered-Vth buffers are able to significantly widen the range of energy-delay trade-offs achievable in real designs, thereby showing improved design flexibility compared to single-Vth buffers. In ad- dition, tapered-Vth buffers are shown to offer an up to energy reduction under a given performance constraint. A circuit-level op- timization procedure including the leakage energy contribution is adopted to explore the entire energy-delay space, in contrast to previous analyses that targeted only a specific point. To this aim, an analytical framework to express the energy-delay trade-off of CMOS buffers is presented, based on the Logical Effort method- ology. Simulations in a 45-nm CMOS technology are extensively performed to validate the approach in a case study (Word Lines buffers for memory arrays) and in a number of other design cases. Extensive simulations are performed to understand the limits of the proposed approach, as well as the impact of the activity rate, the supply voltage, and process variations.