An 8b 100mhz Folding Adc

where N is the number of bits. To maintain the signal-to-noise ratio of an ADC within 3dB of the theoretical value, a timing uncertainty of less than 12ps is needed when the input frequency is 50MHz. Because the physical dimensions of flash converters tend to increase, this uncertainty requirement may result in impractical clock distribution requirements. A folding ADC folds the input signal and uses the same comparators a number of times’. In this way, a large die size reduction is obtained, allowing stringent requirements on the timing distribution of clock and signal lines. Because of the smaller number of comparators, a higher current can be used for each comparator, increasing the analog bandwidth.