Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories

The framework of this article lies in the dynamic management of the reliability in NOR embedded Flash memories (eFlash). The main objective is to build a new reliability management scheme and to predict its efficiency to improve the eFlash reliability using error correction code and redundancy. The originality of the proposed approach relies on the use of a dedicated error correcting code well suited to NOR flash memories operational conditions. This code, named hierarchical code, improves the correction capabilities with a minimal impact on performance and area. The proposed solution furthermore enables selecting different built-in self strategies allowing to tune reliability strategies to the targeted application domain.

[1]  A. Hoefler,et al.  Statistical modeling of the program/erase cycling acceleration of low temperature data retention in floating gate nonvolatile memories , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[2]  Gian Carlo Cardarilli,et al.  Data integrity evaluations of Reed Solomon codes for storage systems [solid state mass memories] , 2004 .

[3]  Bruce F. Cockburn,et al.  Cost models for large file memory DRAMs with ECC and bad block marking , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[4]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[5]  Y. Takeuchi,et al.  A compact on-chip ECC for low cost flash memories , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[6]  Cheng-Wen Wu,et al.  An integrated ECC and redundancy repair scheme for memory reliability enhancement , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[7]  Benoît Godard,et al.  Architecture for Highly Reliable Embedded Flash Memories , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[8]  Cheng-Wen Wu,et al.  A built-in self-repair scheme for NOR-type flash memory , 2006, 24th IEEE VLSI Test Symposium.

[9]  Carla Golla,et al.  Flash Memories , 1999 .

[10]  Alessandro Birolini.  Reliability Engineering: Theory and Practice , 1999 .

[11]  R. Morelos-Zaragoza.  The art of error correcting coding , 2002 .

[12]  Yong-Bin Kim,et al.  Optimal spare utilization in repairable and reliable memory cores , 2003, Records of the 2003 International Workshop on Memory Technology, Design and Testing.

[13]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .