Efficient output ESD protection for 0.5-/spl mu/m high-speed CMOS SRAM IC with well-coupled technique

This work reports an effective ESD protection circuit design for CMOS IC's by using well-coupled field-oxide device (WCFOD). The bipolar action of the field-oxide device is triggered by well-coupling technique. The ESD-trigger voltage of WCFOD is lowered below the snapback-breakdown voltage of an output transistor, so it can perform efficient ESD protection for output transistors. A 0.5-/spl mu/m high-speed 256K SRAM product had been fabricated with this proposed well coupled technique to practically verify the excellent efficiency for output ESD protection. The ESD failure voltage of this SRAM product has been improved up to above 6KV without any extra ESD-Implant, process, whereas the original output buffer just can sustain the HBM ESD stress of 1KV only.