A decimal carry-free adder

Recently, decimal arithmetic has become attractive in the financial and commercial world including banking, tax calculation, currency conversion, insurance and accounting. Although computers are still carrying out decimal calculation using software libraries and binary floating-point numbers, it is likely that in the near future, all processors will be equipped with units performing decimal operations directly on decimal operands. One critical building block for some complex decimal operations is the decimal carry-free adder. This paper discusses the mathematical framework of the addition, introduces a new signed-digit format for representing decimal numbers and presents an efficient architectural implementation. Delay estimation analysis shows that the adder offers improved performance over earlier designs.

[1]  Keshab K. Parhi.  Fast low-energy VLSI binary addition , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[2]  Michael J. Schulte,et al.  Multioperand decimal addition , 2004, IEEE Computer Society Annual Symposium on VLSI.

[3]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[4]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[5]  K. Kaneko,et al.  A CMOS floating point multiplier , 1984, IEEE Journal of Solid-State Circuits.

[6]  D. Gay.  Correctly Rounded Binary-Decimal and Decimal-Binary Conversions , 1990 .

[7]  Michael J. Schulte,et al.  Decimal multiplication via carry-save addition , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[8]  Israel Koren.  Computer arithmetic algorithms , 1993 .

[9]  Paul Jespers,et al.  A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor , 1989 .

[10]  William D. Clinger.  How to read floating point numbers accurately , 1990, PLDI '90.

[11]  A. Weinberger,et al.  High Speed Decimal Addition , 1971, IEEE Transactions on Computers.

[12]  David Y. Y. Yun,et al.  RBCD: redundant binary coded decimal adder , 1989 .

[13]  Keshab K. Parhi,et al.  A fast VLSI adder architecture , 1992 .

[14]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[15]  Jen-Shiun Chiang,et al.  Carry-Free Radix-2 Subtractive Division Algorithm and Implementation of the Divider , 2000 .

[16]  Behrooz Pamami,et al.  Generalized Signed-Digit Number Systems : A Unifying Framework for Redundant Number Representations , 1990 .

[17]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[18]  Reto Zimmermann,et al.  Binary adder architectures for cell-based VLSI and their synthesis , 1997 .