The Test and Verification Influential Papers in the 10 Years of DATE

The history of test is looked at for IC Test to put in context the papers that are being highlighted at DATE. This paper focuses on the path that led to the adoption of structural test. ATE related historical aspects are not mentioned.

[1]  M. Ray Mercer,et al.  Iddq testing for high performance CMOS-the next ten years , 1996, Proceedings ED&TC European Design and Test Conference.

[2]  Bashir M. Al-Hashimi,et al.  Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression , 2002, DATE.

[3]  Rohit Kapur,et al.  A reconfigurable shared scan-in architecture , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[4]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[5]  Giovanni Squillero,et al.  An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[6]  M. Ray Mercer,et al.  Delay Testing Quality in Timing-Optimized Designs , 1991, 1991, Proceedings. International Test Conference.

[7]  M. Ray Mercer,et al.  The interdependence between delay-optimization of synthesized networks and testing , 1991, 28th ACM/IEEE Design Automation Conference.

[8]  M. Ray Mercer,et al.  Statistical delay fault coverage and defect level for delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[9]  Eugene Goldberg,et al.  BerkMin: A Fast and Robust Sat-Solver , 2002 .

[10]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[11]  Lorena Anghel,et al.  Cost reduction and evaluation of temporary faults detecting technique , 2000, DATE '00.

[12]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[13]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.

[14]  Michael S. Hsiao,et al.  Efficient spectral techniques for sequential ATPG , 2001, DATE '01.

[15]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[16]  Zebo Peng,et al.  An integrated system-on-chip test framework , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[17]  Rohit Kapur,et al.  Changing the scan enable during shift , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..