Lifetime maps for two 4H-SiC epi-wafers (samples 1 and 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the type and distribution of structural defects mapped by synchrotron X-ray topography (white beam and monochromatic). Sample 1 showed lower lifetime inside one of its higher doped facet regions and along its edges. The low lifetime in the facet region was associated with the presence of a high density of multi-layered Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). These stacking faults are likely double Shockley stacking faults (DSSFs) and probably nucleated from scratches present on the substrate surface and LAGBs present in that region, propagating during epilayer growth. In contrast, sample 2 showed a reduced carrier lifetime in the middle region associated with a network of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that are generated during epilayer growth. Along the edges of both samples, overlapping triangular defects, microcracks and BPD loops lowered lifetime.