Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography

Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.

[1]  P. L. Montgomery Modular multiplication without trial division , 1985 .

[2]  Keivan Navi,et al.  A Novel Reversible BCD Adder For Nanotechnology Based Systems , 2008 .

[3]  Lei Yang,et al.  An efficient CSA architecture for montgomery modular multiplication , 2007, Microprocess. Microsystems.

[4]  Yang Shi,et al.  A Novel Reversible ZS gate and its Application for Optimization of Quantum Adder Circuits , 2011, J. Circuits Syst. Comput..

[5]  Majid Haghparast,et al.  Design of a New Parity Preserving Reversible Full Adder , 2015, J. Circuits Syst. Comput..

[6]  Majid Haghparast,et al.  Novel Nanometric Reversible Low Power Bidirectional Universal Logarithmic Barrel Shifter with Overflow and Zero Flags , 2015, J. Circuits Syst. Comput..

[7]  Hafiz Md. Hasan Babu,et al.  Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography , 2009 .

[8]  Ahmed Younes,et al.  Tight Bounds on the Synthesis of 3-Bit Reversible Circuits: Nffr Library , 2013, J. Circuits Syst. Comput..

[9]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[10]  Hsie-Chia Chang,et al.  An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  C. D. Walter,et al.  Montgomery exponentiation needs no final subtractions , 1999 .

[12]  Gerhard W. Dueck,et al.  Design and Optimization of Single and Multiple-Loop Reversible and Quantum Feedback Circuits , 2012, J. Circuits Syst. Comput..

[13]  Muhammad Mahbubur Rahman,et al.  Low Cost Quantum Realization of Reversible Multiplier Circuit , 2009 .

[14]  Ahmed Younes,et al.  Reducing Quantum Cost of Reversible Circuits for Homogeneous Boolean Functions , 2010, J. Circuits Syst. Comput..

[15]  Keivan Navi,et al.  Optimized Reversible Multiplier Circuit , 2009, J. Circuits Syst. Comput..

[16]  Anas N. Al-Rabadi Reversible Systolic Arrays: M-Ary Bijective Single-Instruction Multiple-Data (SIMD) Architectures and their Quantum Circuits , 2008, J. Circuits Syst. Comput..

[17]  Seokhie Hong,et al.  Extended elliptic curve Montgomery ladder algorithm over binary fields with resistance to simple power analysis , 2013, Inf. Sci..

[18]  R. Landauer,et al.  The Fundamental Physical Limits of Computation. , 1985 .

[19]  R. Landauer Information is physical , 1991 .

[20]  Kenichi Morita,et al.  Reversible computing and cellular automata - A survey , 2008, Theor. Comput. Sci..

[21]  Babak Sadeghiyan,et al.  High Performance Montgomery Modular Multiplier with a New Recoding Method , 2011, J. Circuits Syst. Comput..

[22]  ÇETIN K. KOÇ,et al.  Montgomery Multiplication in GF(2k) , 1998, Des. Codes Cryptogr..

[23]  Igor L. Markov,et al.  Synthesis and optimization of reversible circuits—a survey , 2011, CSUR.

[24]  P. Kalpana,et al.  Energy Efficient Reversible Building Blocks Resistant to Power Analysis Attacks , 2014, J. Circuits Syst. Comput..

[25]  Guowu Yang,et al.  Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.