Chapter 14 – Other Cortex-M3 Features

Publisher Summary This chapter emphasizes various Cortex-M3 features such as the SYSTICK timer power management, multiprocessor communication, and self-reset control. The Cortex-M3 processor allows two different clock sources for the SYSTICK counter. The first one is the core free-running clock, i.e., not from the system clock HCLK, so it does not stop when the system clock is stopped. The second one is an external reference clock. This clock signal must be at least two times slower than the free-running clock because the free-running clock samples this signal. Because a chip designer might decide to omit this external reference clock in the design, it might not be available. To determine whether the external clock source is available, one should check bit[31] of the SYSTICK Calibration register. The chip designer should connect this pin to an appropriate value based on the design. In self-reset control of the Cortex-M3 processor, there are two features. The first one is the VECTRESET control bit in the NVIC Application Interrupt and Reset Control register and the second reset feature is the SYSRESETREQ bit in the same NVIC register. It allows the Cortex-M3 processor to assert a reset request signal to the system's reset generator. Since the system reset generator is not part of the Cortex-M3 design, the implementation of this reset feature depends on the chip design. Therefore, it is necessary to carefully check the chip's specification.