Buffer insertion under process variations for delay minimization
暂无分享,去创建一个
[1] Martin D. F. Wong,et al. A graph based algorithm for optimal buffer insertion under accurate delay models , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[2] L.P.P.P. van Ginneken,et al. Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .
[3] S. Nassif,et al. Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[4] David Blaauw,et al. Variational delay metrics for interconnect timing analysis , 2004, Proceedings. 41st Design Automation Conference, 2004..
[5] Liang Deng,et al. An exact algorithm for the statistical shortest path problem , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[6] Kurt Keutzer,et al. Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Charles J. Alpert,et al. Wire segmenting for improved buffer insertion , 1997, DAC.
[8] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[9] Sani R. Nassif. Modeling and forecasting of manufacturing variations , 2000, 2000 5th International Workshop on Statistical Metrology (Cat.No.00TH8489.
[10] Azadeh Davoodi,et al. A Probabilistic Approach to Buffer Insertion , 2003, ICCAD 2003.
[11] Sani R. Nassif. Modeling and forecasting of manufacturing variations (embedded tutorial) , 2001, ASP-DAC '01.
[12] William J. Bowhill,et al. Design of High-Performance Microprocessor Circuits , 2001 .
[13] James Tschanz,et al. Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).