Power Optimization Techniques

This chapter contains sections titled: Technology Mapping for Low Power POSE: Power Optimization and Synthesis Environment Transformation and Synthesis of FSMs for Low-Power Gated-Clock Implementation Precomputation-Based Sequential Logic Optimization for Low Power Glitch Analysis and Reduction in Register Transfer Level Power Optimization Exploiting Locality for Low-Power Design HYPER-LP: A System for Power Minimization Using Architectural Transformations Scheduling with Multiple Voltages System-Level Transformations for Low Power Data Transfer and Storage