Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parameters

Crosstalk-induced noise of 0.18 /spl mu/m CMOS Technology is characterized using time domain reflectometry and scattering parameters. The interconnect lines are quantitatively modeled in RF range, whose accuracy was verified with the use of TDR data and its comparison with HSPICE simulation. The modeled interconnect line is used to simulate comprehensively crosstalk-induced noise voltage in various real routing environments using HSPICE. The crosstalk voltage exhibited a strong dependence on line width rather than line space.

[1]  Jeong-Mo Hwang,et al.  Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging , 1998 .

[2]  Keh-Jeng Chang,et al.  2001 needs for multi-level interconnect technology , 1995 .

[3]  N.H. Kim,et al.  Interconnect capacitance, crosstalk, and signal delay for 0.35 /spl mu/m CMOS technology , 1996, International Electron Devices Meeting. Technical Digest.

[4]  K. Yamashita,et al.  Impact of crosstalk on delay time and a hierarchy of interconnects , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[5]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[6]  Hi-Deok Lee,et al.  Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).