Architectural Selection Using High Level Synthesis

Advances in semiconductor technology still governed by Moore’s law, have enhanced our ability to create extremely large and complex microelectronic systems. To utilize the increased number of transistors on a single chip, and to cope with the ever increasing demand for more functionalities in electronic systems, system-on-chip (SoC) based designs are being increasingly used. A growing trend in SoC design is to have heterogeneous processors on a single chip. In the embedded systems domain, a common performance enhancement strategy is to use dedicated co-processors on which the main processor can off-load compute intensive tasks. Compute intensive tasks such as encryption, decryption, compression, matrix multiplication, etc., were earlier done using software on the main processor. Therefore, a large number of sophisticated software algorithms exist and are often available in very efficient C-based implementations. Since time-to-market windows are forever shortening, reuse has become a mantra in the industry. Why not reuse efficient, well validated, and time tested software algorithms, and synthesize automatically for power/energy, area, and latency efficient implementations? Such a path to hardware would spare the designers the excessive time required to develop the co-processors from scratch as well as reduce the resources required to verify the hardware in RTL simulation, which is quite slow. With this goal in mind, we present here C2R compiler based [1] methodology for reusing existing C-based implementation of compute intensive algorithms. We also present, how one can systematically carry out architectural exploration at the C-level and automatically synthesize efficient hardware co-processors.