VLSI reliability challenges: from device physics to wafer scale systems

Abstract The philosophical and practical differences between Japanese and American IC industries concerning VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing are discussed. A new challenging approach to VLSI reliability is now greatly needed in response to the “paradigm shift” now being brought about by simple scaling limitations, increased process complexity, and VLSI application to advanced systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the “building-in-reliability” approach. To pursue this technique, greater importance will be attached to a deeper physical understanding (including frequent use of Computer Aided Design, CAD/ Design Automation, DA) of the significant relationships between the input variables and product reliability, and to total concurrent engineering from research labs to production sites. In addition, distributive quality control management being carried out particularly in Japan, where quality improvement is the common concern for every employeee, may be a key factor in overcoming the more difficult reliability problems in the coming giga-scale ICs. Furthermore, fast new VLSI testing methods and new yield-enhancing redundancy techniques, resulting in cost reduction, will be increasingly needed to achieve high reliability for VLSIs with 109 devices on a single chip.