An 800Mbps Quasi-Cyclic LDPC Decoder Implementation with FPGA

This paper presents a low-complexity,high-speed encoder architecture for QC-LDPC code.In the design,the character of circulant matrix is employed to increase the parallelism of encoder through the introduction of small hardware overhead.A type of encoding circuits using parallel architectures of shift-register-adder-accumulator(SRAA) is designed to increase the throughput of encoders. A major feature of the high speed encoding is that it has an extremely low latency and low complexity.Results show that the proposed encoder for an(8176,7154) Finite Geometries LDPC code can achieve an information encoding throughput over 800 Mbps on Xilinx Virtex 4 FPGA.