Design of a stable single sided 11T static random access memory cell with improved critical charge

Radiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge‐boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft‐error‐immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13×/1.38×/0.90×/1.04×/1.03× improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31×/1.17×/1.31×/1.41×/1.01× compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97×/0.98×/1.91×/1.24×/1× when equated to 6T/PP10T/AS8T/Quatro10T/LC10T cell. Improved Inter‐cell and Intra‐cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.

[1]  Ashish Sachdeva,et al.  Design of a soft error hardened SRAM cell with improved access time for embedded systems , 2022, Microprocess. Microsystems.

[2]  M. Hasan,et al.  Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications , 2021, 2021 25th International Symposium on VLSI Design and Test (VDAT).

[3]  Ashish Sachdeva,et al.  Characterization of Stable 12T SRAM with Improved Critical Charge , 2021, J. Circuits Syst. Comput..

[4]  Ashish Sachdeva,et al.  Noise margin enhancement of Conventional 6T SRAM Cell by aspect Ratio Optimization , 2021, 2021 10th IEEE International Conference on Communication Systems and Network Technologies (CSNT).

[5]  Ashish Sachdeva,et al.  A soft-error resilient low power static random access memory cell , 2021, Analog Integrated Circuits and Signal Processing.

[6]  Ashish Sachdeva,et al.  A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications , 2021, Wireless Personal Communications.

[7]  Ashish Sachdeva,et al.  Design of 10T SRAM cell with improved read performance and expanded write margin , 2020, IET Circuits Devices Syst..

[8]  Vinay Tomar,et al.  A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era , 2020, Wireless Personal Communications.

[9]  Vinay Tomar,et al.  Design of Low Power Half Select Free 10T Static Random-Access Memory Cell , 2020, J. Circuits Syst. Comput..

[10]  Vishal Sharma,et al.  An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application , 2020, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields.

[11]  Santosh Kumar Vishvakarma,et al.  Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications , 2020, J. Electron. Test..

[12]  M. Waltl,et al.  Bias Temperature Instability Aware and Soft Error Tolerant Radiation Hardened 10T SRAM Cell , 2020 .

[13]  Wing-Hung Ki,et al.  A highly stable reliable SRAM cell design for low power applications , 2020 .

[14]  Santosh Kumar Vishvakarma,et al.  Process Variation and NBTI Resilient Schmitt Trigger for Stable and Reliable Circuits , 2018, IEEE Transactions on Device and Materials Reliability.

[15]  Massoud Pedram,et al.  Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs , 2018, IET Circuits Devices Syst..

[16]  Hai Huang,et al.  Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Jie Li,et al.  Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Le Dinh Trang Dang,et al.  We-Quatro: Radiation-Hardened SRAM Cell With Parametric Process Variation Tolerance , 2017, IEEE Transactions on Nuclear Science.

[19]  Huaguo Liang,et al.  Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Sied Mehdi Fakhraie,et al.  A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  M. Gaillardin,et al.  Modeling Single Event Transients in Advanced Devices and ICs , 2015, IEEE Transactions on Nuclear Science.

[22]  B. L. Bhuva,et al.  Impact of Technology Scaling on SRAM Soft Error Rates , 2014, IEEE Transactions on Nuclear Science.

[23]  Ming-Hsien Tu,et al.  40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Samar K. Saha,et al.  Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design , 2014, IEEE Access.

[25]  Enrico Macii,et al.  Dynamic Indexing: Leakage-Aging Co-Optimization for Caches , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[27]  Sorin Cotofana,et al.  Variation tolerant on-chip degradation sensors for dynamic reliability management systems , 2012, Microelectron. Reliab..

[28]  David Blaauw,et al.  Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Shunsuke Okumura,et al.  A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[30]  Mohd. Hasan,et al.  A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell , 2012, Microelectron. Reliab..

[31]  Y. Bentoutou,et al.  A Real Time EDAC System for Applications Onboard Earth Observation Small Satellites , 2012, IEEE Transactions on Aerospace and Electronic Systems.

[32]  Kaushik Roy,et al.  A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[33]  Meng-Fan Chang,et al.  A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications , 2011, IEEE Journal of Solid-State Circuits.

[34]  Shi-Yu Huang,et al.  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation , 2011, IEEE Journal of Solid-State Circuits.

[35]  Honda Kentaro,et al.  Elimination of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor , 2010 .

[36]  Meng-Fan Chang,et al.  A large σVTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme , 2010, 2010 Symposium on VLSI Circuits.

[37]  Shuhei Tanakamaru,et al.  70% read margin enhancement by VTH mismatch self-repair in 6T-SRAM with asymmetric pass gate transistor by zero additional cost, post-process, local electron injection , 2010, 2010 Symposium on VLSI Circuits.

[38]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[39]  S. Jahinuzzaman,et al.  A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability , 2009, IEEE Transactions on Nuclear Science.

[40]  A.P. Chandrakasan,et al.  A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[41]  Mohammad Sharifkhani,et al.  An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[42]  Abhijit Chatterjee,et al.  Accurate Linear Model for SET Critical Charge Estimation , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[43]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[44]  C.H. Kim,et al.  A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode , 2008, IEEE Journal of Solid-State Circuits.

[45]  Kaushik Roy,et al.  A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[46]  Bo Zhai,et al.  A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM , 2008, IEEE Journal of Solid-State Circuits.

[47]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[48]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[49]  C.H. Kim,et al.  A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing , 2008, IEEE Journal of Solid-State Circuits.

[50]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[51]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[52]  Dieter K. Schroder,et al.  Negative bias temperature instability: What do we understand? , 2007, Microelectron. Reliab..

[53]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[54]  B.L. Bhuva,et al.  Charge Collection and Charge Sharing in a 130 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.

[55]  Rong Luo,et al.  Modeling the Impact of Process Variation on Critical Charge Distribution , 2006, 2006 IEEE International SOC Conference.

[56]  B. Granbom,et al.  Soft error rate increase for new generations of SRAMs , 2003 .

[57]  H. Hughes,et al.  Radiation effects and hardening of MOS technology: devices and circuits , 2003 .

[58]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[59]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[60]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[61]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[62]  H. Shinohara,et al.  A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM , 1983, IEEE Journal of Solid-State Circuits.

[63]  Ashish Sachdeva,et al.  Design of multi-cell upset immune single-end SRAM for low power applications , 2021 .

[64]  Mohammad Gholami,et al.  Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write Path , 2019, Circuits Syst. Signal Process..

[65]  Ahmed M. Eltawil,et al.  AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement , 2017, IET Circuits Devices Syst..

[66]  Mathias Beike,et al.  Digital Integrated Circuits A Design Perspective , 2016 .