On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress
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[1] C. Duvvury,et al. Lateral DMOS design for ESD robustness , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[2] Ming-Dou Ker,et al. The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs , 2005 .
[3] Steven H. Voldman,et al. Latchup in CMOS technology , 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).
[4] Ming-Dou Ker. Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology , 1998 .
[5] Ming-Dou Ker,et al. ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications , 2005, Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005..
[6] N. Boswell. Vacuum fluorescent display developments , 1989 .
[7] Chung-Yu Wu,et al. Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI , 1996 .
[8] Ming-Dou Ker,et al. How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on , 1999 .
[9] Bart Keppens,et al. ESD protection solutions for high voltage technologies , 2004 .
[10] Philippe Perdu,et al. Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology , 2001 .
[11] Chung-Yu Wu,et al. Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation , 1995 .
[12] B. Keppens,et al. Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).
[13] Michael C. Smayling,et al. Device integration for ESD robustness of high voltage power MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.
[14] Taylor R. Efland,et al. SCR-LDMOS. A novel LDMOS device with ESD robustness , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).
[15] R. Y. Shiue,et al. Novel ESD protection structure with embedded SCR LDMOS for smart power technology , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[16] A. Slack. Prospective developments in automotive instrumentation , 1998, Twenty Second IEEE/CPMT International Electronics Manufacturing Technology Symposium. IEMT-Europe 1998. Electronics Manufacturing and Development for Automotives (Cat. No.98CH36204).
[17] Wolfgang Fichtner,et al. Analysis of lateral DMOS power devices under ESD stress conditions , 2000 .
[18] Chung-Yu Wu,et al. Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation , 1995 .
[19] M. Ker. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .