A digital IC Random Number Generator with logic gates only

Random Number Generators with logic gates only are popular among digital IC designers in terms of their speed compatibility and uncomplicated integration to digital platforms. To the best of our knowledge, this paper presents the first ASIC implementation of a Random Number Generator based on Fibonacci and Galois ring oscillators. Prototypes have been designed and fabricated by using HHNEC's 0.25µm eFlash process with a supply voltage of 2.5V. Fibonacci and Galois ring oscillators are implemented in combined configuration. A combined configuration, which consists of a Fibonacci ring oscillator with 16 inverters and a Galois ring oscillator with 32 inverters, occupies 0.0048mm2 and dissipates 2.5mW of power which is quite small compared to other well-known random number generators based on digital circuitry. IC design level experiences, measurements, analysis of measurements and statistical test results are also demonstrated. Furthermore, we propose to use several of these oscillators in an xored configuration, in order to speed up and improve the quality of the generated bit stream. We could achieve fulfilled test results from NIST 800-22 test suit after Von Neumann corrector for 7 xored Fibonacci and Galois ring oscillators with a sampling frequency of 125MHz and 31.25Mbps throughput. In addition, increasing the number of xored Fibonacci and Galois ring oscillators from 7 to 8 also fulfills the tests of NIST 800-22 at the same sampling frequency however, without any further post processing. Thus, 125Mbps of throughput, which is the highest data rate to date with fulfilled test results, could be obtained.

[1]  Ingrid Verbauwhede,et al.  FPGA Vendor Agnostic True Random Number Generator , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[2]  uz,et al.  Truly random number generators based on non-autonomous continuous-time chaos , 2010 .

[3]  Marco Bucci,et al.  A Design of Reliable True Random Number Generator for Cryptographic Applications , 1999, CHES.

[4]  L. Kocarev,et al.  Chaos-based random number generators-part I: analysis [cryptography] , 2001 .

[5]  Jovan Dj. Golic,et al.  High-Speed True Random Number Generation with Logic Gates Only , 2007, CHES.

[6]  Paul B. Garrett.  Making, Breaking Codes : Introduction to Cryptology , 2001 .

[7]  Olivier Sentieys,et al.  On-the-Fly Evaluation of FPGA-Based True Random Number Generator , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[8]  J.D. Golic,et al.  New Methods for Digital Generation and Postprocessing of Random Data , 2006, IEEE Transactions on Computers.

[9]  Berk Sunar,et al.  A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks , 2007, IEEE Transactions on Computers.

[10]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[11]  Johan A. K. Suykens,et al.  True random bit generation from a double-scroll attractor , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Young-Sik Kim,et al.  Fast Digital TRNG Based on Metastable Ring Oscillator , 2008, CHES.

[13]  J. Alvin Connelly,et al.  A noise-based IC random number generator for applications in cryptography , 2000 .

[14]  R. Rovatti,et al.  Embeddable ADC-based true random number generator for cryptographic applications exploiting nonlinear signal processing and chaos , 2005 .

[15]  Alessandro Trifiletti,et al.  A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC , 2003, IEEE Trans. Computers.